This disclosure relates to data processing and storage, and more specifically, to reducing error correction latency in a data storage system having lossy storage media, such as flash memory.
Flash memory is a non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor. FIG. 1 illustrates a conventional flash memory system 100, which includes one or more flash modules 102 each including multiple flash die 104 (only one of which is illustrated). Each flash die 104 in turn includes a flash array 106, which includes a plurality of memory cells for storing one or more bits of data, and an input/output (I/O) buffer 108, which temporarily buffers data read from and written into flash array 106. The operation of the flash module(s) 102 and read and write accesses to flash array 106 are controlled by an external flash controller 110 typically coupled to flash module 102 by a communication bus. Flash controller 110 includes an error correcting code (ECC) circuit 112 that detects and corrects errors in the data read from flash array 106 by reference to error correcting codes (ECC) stored in flash array 106 in conjunction with the data.
As shown in FIG. 1, in a conventional flash memory, a read operation is comprised of a number of distinct suboperations, including 1) a fetch suboperation that fetches a granule of data and associated ECC stored within flash array 106 into an I/O buffer 108 within the same flash die 104 as the flash array 106, 2) a transfer suboperation that transfers the data granule and associated ECC from I/O buffer 108 to ECC circuit 112 of the external flash controller 110 via the external communication bus connecting flash module 102 and flash controller 110, 3) an error detection and correction suboperation in which ECC circuit 112 detects any bit error(s) in the data granule and, if possible, corrects the bit error(s), if any, and 4) a forward (or unload) operation in which flash controller 110 forwards the data granule, as corrected, to a destination. These four suboperations are generally serialized and do not overlap in time.
Referring now to FIG. 2, there is depicted a block diagram of an alternative flash memory system 200 in accordance with the prior art. Flash memory system 200 includes one or more flash modules 202 each including multiple flash die 204 (only one of which is illustrated). Each flash die 204 in turn includes a flash array 206, which includes a plurality of memory cells for storing one or more bits of data, and an input/output (I/O) buffer 208, which temporarily buffers data read from and written into flash array 206. In contrast to flash memory system 100 of FIG. 1, control is implemented in flash memory system 200 of FIG. 2 by a small internal controller 210 integrated within each flash module 202 rather than by an external flash controller 110. The integration of NAND flash die and error correction circuitry in a single package in this manner is sometimes referred to as “managed NAND.” Internal controller 210 includes an ECC circuit 212 that detects and corrects errors in the data read from flash array 206 by reference to error correcting codes (ECC) stored in flash array 206 conjunction with the data.
In flash memory system 200, the suboperations of a read operation, while essentially the same as those performed in flash memory system 100 of FIG. 1, are performed slightly differently given the architectural differences. In particular, the transfer suboperation transfers data and the associated ECC from I/O buffer 208 in flash die 204 to the internal controller 210 disposed within the same device package as the flash die 204. In addition, the error detection and correction suboperation is performed by an ECC circuit 212 co-located within the flash module 202 (rather than in an external flash controller 110), and the final forward suboperation forwards the corrected data granule across the external I/O bus of flash module 202 rather than the I/O bus of external flash controller 110, which typically has a much greater bandwidth.
With reference now to FIG. 3, a timing diagram is given that illustrates the relative read latencies for conventional flash memory systems 100 and 200. The read operation of flash memory system 100 includes fetch suboperation 300, transfer suboperation 302, detect and correct suboperation 304 and forward suboperation 306, and the read operation of flash memory system 200 includes corresponding suboperations 310, 312, 314 and 316, respectively. Due to the serialization of the suboperations, the total latency of each of the read operations can be computed simply by aggregating the latencies of the suboperations.
As indicated, a flash memory system 200 having managed NAND flash can generally complete the fetch and transfer suboperations 310 and 312 more quickly than the corresponding suboperations 300, 302 of flash memory system 100 given the proximity of internal controller 210 to flash die 204. However, the overall read latency of a flash memory system 100 having an dedicated external flash controller 110 is generally lower because flash controller 110 has a forwarding bandwidth many times greater than the I/O bandwidth of a single flash module 202. In addition, an external flash controller 110 often includes an ECC circuit 112 that is far more powerful and significantly faster than the analogous ECC circuit 212, which must be sized small enough to be integrated into a flash memory device package with the flash die 204.